{"created":"2023-06-19T11:40:39.763046+00:00","id":9120,"links":{},"metadata":{"_buckets":{"deposit":"ddf0a39a-18dc-4be5-beee-642f7ced67c4"},"_deposit":{"created_by":15,"id":"9120","owners":[15],"pid":{"revision_id":0,"type":"depid","value":"9120"},"status":"published"},"_oai":{"id":"oai:mie-u.repo.nii.ac.jp:00009120","sets":["366:640:641:647"]},"author_link":["22778","22777"],"item_7_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2011-01-01","bibliographicIssueDateType":"Issued"}}]},"item_7_contributor_61":{"attribute_name":"修士論文指導教員","attribute_value_mlt":[{"contributorNames":[{"contributorName":"近藤, 利夫","lang":"ja"}],"nameIdentifiers":[{"nameIdentifier":"22778","nameIdentifierScheme":"WEKO"}]}]},"item_7_description_14":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_7_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Enhancement of mobile computers requires the achievement of high performance computing with low energy consumption. Variable stages pipeline (VSP) architecture, which reduces energy consumption and improves execution time by dynamically unifying the pipeline stages, is proposed to achieve this requirement. To unify the pipeline stages dynamically, the VSP processor adopts a special pipeline register called the LDS-cell (Latch D-flip flop Selector-cell). The LDS-cell does not only unify the pipeline stages but can also prevent glitch propagation caused by stage unification under low energy mode. In this paper, the design of the fabricated VLSI of the VSP processor chip on a 0.18 ?m CMOS technology is described. Evaluation of the energy consumption shows that the VSP processor can achieve 13% Iess eners/ consumption than the conventional approach.","subitem_description_type":"Abstract"}]},"item_7_description_5":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"三重大学大学院工学研究科博士前期課程情報工学専攻","subitem_description_type":"Other"},{"subitem_description":"12","subitem_description_type":"Other"}]},"item_7_publisher_30":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"三重大学"}]},"item_7_text_65":{"attribute_name":"資源タイプ（三重大）","attribute_value_mlt":[{"subitem_text_value":"Master's Thesis / 修士論文"}]},"item_7_version_type_15":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"中林, 智之","creatorNameLang":"ja"}],"nameIdentifiers":[{"nameIdentifier":"22777","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-02-20"}],"displaytype":"detail","filename":"2010M240.pdf","filesize":[{"value":"3.4 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"2010M240.pdf","url":"https://mie-u.repo.nii.ac.jp/record/9120/files/2010M240.pdf"},"version_id":"e7edda3f-cb3a-4375-9ed4-d9ea6ce4c02d"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"thesis","resourceuri":"http://purl.org/coar/resource_type/c_46ec"}]},"item_title":"低消費電力と高性能を実現するTSPC DFFを用いた可変段数パイプラインプロセッサの改良手法に関する研究","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"低消費電力と高性能を実現するTSPC DFFを用いた可変段数パイプラインプロセッサの改良手法に関する研究","subitem_title_language":"ja"}]},"item_type_id":"7","owner":"15","path":["647"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2013-06-11"},"publish_date":"2013-06-11","publish_status":"0","recid":"9120","relation_version_is_last":true,"title":["低消費電力と高性能を実現するTSPC DFFを用いた可変段数パイプラインプロセッサの改良手法に関する研究"],"weko_creator_id":"15","weko_shared_id":-1},"updated":"2023-09-11T01:42:32.662504+00:00"}